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msM5259 ? semiconductor 1/18 general description the msM5259 is a dot matrix lcd segment driver which is fabricated using low power cmos metal gate technology. this lsi consists of 40-bit shift register, 40-bit latch and 40-bit 4-level driver. it converts serial data, which is received from an lcd controller lsi, to parallel data and outputs lcd driving waveforms to lcd. expansion of the display can be easily made according to the number and structure of characters. since the 40-bit shift register of this device consists of two 20-bit shift registers, it is possible to allot bits efficiently according to the number of characters. the msM5259 can drive a variety of lcd panels because the bias voltage, which determines the lcd driving voltage, can be optionally supplied from the external source. for static operation only, the device is available with a power supply voltage of 2.5v or more. features ? supply voltage : 3.5 to 6.0v (dynamic display) : 2.5 to 6.0v (static display) ? lcd driving voltage : 2.5 to 6.0v (static display) ? applicable lcd duty : 1/8 to 1/16 ? interface with msm6222-xx (dot matrix lcd controller with 16-dot common driver and 40- dot segment driver) ? bias voltage can be supplied externally. ? package options: 56-pin plastic qfp (qfp56-p-910-0.65-k) (product name : msM5259gs-k) 56-pin plastic qfp (qfp56-p-910-0.65-l2) (product name : msM5259gs-l2) 56-pin plastic qfp (qfp56-p-910-0.65-2k) (product name : msM5259gs-2k) 56-pin plastic qfp (qfp56-p-910-0.65-2l2) (product name : msM5259gs-2l2) ? semiconductor msM5259 40-dot segment driver e2b0019-27-y2 this version: nov. 1997 previous version: mar. 1996
msM5259 ? semiconductor 2/18 block diagram o 1 o 2 o 19 o 20 o 21 o 22 o 40 o 39 v dd v 2 v 3 v 5 df load di 1 cp do 20 di 21 v ss do 40 40-bit 4-level driver 40-bit latch 20-bit shift register 20-bit shift register
msM5259 ? semiconductor 3/18 pin configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 4 3 2 1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 40 41 42 38 37 36 35 34 33 32 31 30 29 o 1 di 21 do 20 v 5 v 2 load v dd di 1 df nc nc nc o 27 o 26 o 24 o 23 o 21 *(v dd ) o 20 o 18 o 17 o 16 o 15 o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9 o 10 o 11 do 40 o 40 o 39 o 38 o 37 o 36 o 35 o 34 o 33 o 32 o 31 o 12 o 30 o 13 o 29 o 14 o 28 o 19 o 22 o 25 v ss v 3 cp (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 53 54 55 56 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 18 17 16 15 19 20 21 22 23 24 25 26 27 28 nc o 14 o 13 o 12 o 10 o 5 o 8 o 6 o 4 o 3 o 2 o 1 o 28 o 29 o 31 o 32 o 34 o 35 o 36 o 38 o 39 o 40 do 40 nc nc df load di cp v dd v ss v 2 v 3 o 15 o 16 o 17 o 18 o 19 o 20 *(v dd ) o 21 o 22 o 23 o 24 v 5 o 25 do 20 o 26 di 21 o 27 o 37 o 33 o 30 o 9 o 11 o 7 nc : no connection 56-pin plastic qfp (type l) nc : no connection 56-pin plastic qfp (type k) * do not connect pin 21 to the other signal pins, because the pin is internally connected to v dd . do not use pin 21 as a single v dd signal line. it is permissible to use pin 21 for supplying a higher power of v dd . note : the figure for type l shows the configuration viewed from the reverse side of the package. pay attention to the difference in pin arrangement.
msM5259 ? semiconductor 4/18 absolute maximum ratings parameter supply voltage (1) symbol condition rating unit v dd C0.3 to +6.5 v supply voltage (2) v dd C v 5 ta = 25c 0 to +6.5 v input voltage v i C0.3 to v dd +0.3 v storage temperature t stg C55 to +150 c *1 recommended operating conditions parameter supply voltage (1) symbol condition rnage unit v dd 3.5 to 6.0 v static 2.5 to 6.0 supply voltage (2) v dd C v 5 2.5 to 6.0 v operating temperature t op C30 to +85 c dynamic *1 *2 *1 v dd > v 2 > v 3 > v 5 > v ss (dynamic display) v dd = v 3 > v 2 = v 5 = v ss (static display) for v dd of less than 3.5v, the device is available only for static operation. *2 v dd is the reference potential for the lcd driving voltage. to determine the lcd driving voltage, change the value of v 5 . (0v minimum)
msM5259 ? semiconductor 5/18 electrical characteristics dc characteristics (1) 2 3 1 3 parameter "h" input voltage symbol condition min. typ. max. unit v ih 0.8v dd v dd v "l" input voltage v il 0 0.2v dd v "h" input current i ih v ih = v dd 1 m a "l" input current i il v il = 0v C1 m a "h" output voltage v oh i o = C40 m a 4.2 v "l" output voltage v ol i o = 0.4ma 0.4 v on resistance r on v dd Cv 5 = 5v |v n Cv o | = 0.25v 5 k w supply current i dd f cp = 0hz, no load 0.5 ma *1 *1 *1 *1 *2 *2 *3 *4 (v dd = 5v10%, ta=C30 to +85c) *1 applicable to df, load, di 1 and di 21 . *2 applicable to do 20 and do 40 . *3 applicable to o 1 to o 40 . *4 dynamic display : v n = v dd to v 5 , v 2 = (v dd C v 5 ), v 3 = (v dd C v 5 ) static display : v n = v dd to v 5 , v 3 = v dd , v 2 = v 5 = v ss dc characteristics (2) (only for static operation) parameter "h" input voltage symbol condition min. typ. max. unit v ih 0.8v dd v dd v "l" input voltage v il 0 0.2v dd v "h" input current i ih v ih = v dd 1 m a "l" input current i il v il = 0v C1 m a "h" output voltage v oh i o = C40 m a 2.2 v "l" output voltage v ol i o = 0.2ma 0.4 v on resistance r on v 3 = v dd = 3v, v 2 = v 5 = v ss = 0v, | v n Cv o | = 0.25v 10k w supply current i dd f cp = 0hz, no load 0.5 ma *1 *1 *1 *1 *5 *5 *6 (v dd = 3v0.5v, ta=C30 to +85c) *5 applied to do 20 and do 40 . *6 applied to o 1 to o 40 .
msM5259 ? semiconductor 6/18 switching characteristics (1) parameter "h", "l" propagation delay time symbol condition min. typ. max. unit t plh, t phl 250 ns clock frequency f cp duty = 50% 3.3 mhz clock pulse width t w (cp) 125 ns load pulse width t w (l) 125 ns data set-up time di ? cp t setup 50ns data hold time di ? cp t hold 50ns (v dd = 5v10%, ta=C30 to +85c, c l =15pf) cp ? load set-up time t cl 250 ns load ? cp hold time t lc 0ns cp rise/fall time t r(cp) , t f (cp) 50ns load rise/fall time t r(l) , t f(l) 1 m s switching characteristics (2) parameter "h", "l" propagation delay time symbol condition min. typ. max. unit t plh, t phl 800 ns clock frequency f cp duty = 50% 1.0 mhz clock pulse width t w (cp) 300 ns load pulse width t w (l) 300 ns di ? cp set-up time t setup 200 ns di ? cp hold time t hold 200 ns (v dd = 3v0.5v, ta=C30 to +85c, c l =15pf) cp ? load set-up time t cl 800 ns load ? cp hold time t lc 0ns cp rise/fall time t r(cp) 1 m s load rise/fall time t r(l) , t f(l) 1 m s (only for static operation)
msM5259 ? semiconductor 7/18 cp di 21 do 40 load 0.8v dd t w (cp) 0.8v dd t f (cp) t w (cp) 0.2v dd t r (cp) 0.8v dd 0.2v dd 0.8v dd 0.2v dd 0.8v dd 0.8v dd 0.2v dd 0.2v dd 0.8 0.8 v dd v dd 0.2 0.2 v dd v dd t hold t setup t hold t setup 0.8v dd 0.2v dd t plh t phl t cl 0.2v dd 0.2v dd t lc t w (l) t r (l) t f (l) di 1 do 20 0.8v dd 0.8v dd
msM5259 ? semiconductor 8/18 timing diagram 1/5 bias, 1/16 duty frame signal load latch data df df load di cp latch data load latch data df v dd v a v b v c v d v e v lcd 16 1 2 3 16 1 2 3 h l hhhh ll l v 2 v dd v 3 v 5 r r r r r vr v dd v a v b v c v d v e v lcd v a = v dd C v lcd 5 1 C v b = v dd C v lcd 5 2 C v c = v dd C v lcd 5 3 C v d = v dd C v lcd 5 4 C v e = v dd C v lcd v lcd = lcd driving voltage v ss msM5259
msM5259 ? semiconductor 9/18 static display v dd v dd v 3 v 5 v ss v 2 o 40 df o 1 bias supply pin common signal v dd v ss df output (lighting on) output (lighting off) v dd , v 3 v ss , v 5 , v 2 v dd , v 3 v ss , v 5 , v 2
msM5259 ? semiconductor 10/18 functional description pin functional description ?di 1 the data (1st to 20th bit) from the lcd controller lsi is input to 20-bit shift register from di 1 . (positive logic) ?di 21 data input to the shift register (21st to 41st bit). connecting do 20 and di 21 allows configuration of a 40-bit register. if di 21 is not used, connect this pin to v ss . ?cp clock pulse input pin for the two 20-bit shift registers. the data is input to the 20-bit shift register at the falling edge of the clock pulse. a data set up time (t setup ) and data hold time (t hold ) are required between the di1 and di21 signals and a clock pulse. ?do 20 20th bit of the shift register contents is output from do 20 . the data which was input from di 1 is output from this pin with a delay of the number of bits of the shift register (20), synchronized with the clock pulse. by connecting do 20 to di 21 , two 20-bit shift registers can be used as a 40-bit shift register. ?do 40 40th bit of the shift register contents is output from do 40 . the data which was input from di 21 is output from this pin with a delay of the number of bits of the shift register (20), synchronized with the clock pulse. by connecting do 40 to the next msM5259s di 1 , this lsi is applicable to a wide screen lcd. refer to the application circuit. ?df alternate signal input pin for lcd driving. ? load signal for latching the shift register contents is input from this pin. when the load pin is set at "h" level, the shift register contents are transferred to the 40-bit 4-level driver. when load pin is set at "l" level, the last display output data (o 1 - o 40 ), which was transferred when load pin was at "h" level, is held. ?v dd , v ss supply voltage pins. v dd is generally set to 4.0 to 6.0v. v ss is a ground pin (v ss = 0v) ?v 2 , v 3 , v 5 bias supply voltage pins to drive the lcd. bias voltage divided by the register is usually used as supply voltage source. refer to the application circuit. for static operation, connect v 3 to v dd and also connect v 2 , v 5 , to v ss .
msM5259 ? semiconductor 11/18 latched data df driver output level "h" (select) hv 5 lv dd "l" (non-select) hv 3 lv 2 ?o 1 to o 40 display data output pin which corresponds to each data bit in the latch. one of v dd , v 2 , v 3 and v 5 is selected as a display driving voltage source according to the combination of latched data level and df signal. (refer to the truth table below.) truth table
msM5259 ? semiconductor 12/18 common o 1 o 2 o 3 o 4 o 5 o 6 o 7 o 8 o 9 o 10 o 11 o 12 o 13 o 14 o 15 o 16 v dd v a v b v c v d v e o 1 o 2 o 1 o 2 v dd v a v b v c v d v e o 1 o 2 o 3 o 4 o 5 segment v a = v dd C v lcd 5 1 C v b = v dd C v lcd 5 2 C v c = v dd C v lcd 5 3 C v d = v dd C v lcd 5 4 C v e = v dd C v lcd v lcd v lcd 5 3 C v lcd 5 1 C o Cv lcd C v lcd 5 1 C C v lcd 5 3 C v dd v a v b v c v d v e v dd v a v b v c v d v e v lcd v lcd 5 1 C o Cv lcd C v lcd 5 1 C common o 1 -segment o 1 (select waveform) common o 2 -segment o 1 (non-select waveform) 1 frame v lcd 1 2 3 4 16 1 lcd driving waveform (1/5 bias, 1/16 duty)
msM5259 ? semiconductor 13/18 application circuits (connected to msm6222b-01 lcd controller) lcd com 1-16 seg 1-40 do msm6222b-01 msM5259 v dd v ss v 2 v 3 v 5 cp l df v dd gnd v 1 v 2 v 3 v 4 v 5 o 1 -o 40 df cp load di 1 do 20 di 21 do 40 msM5259 v dd v ss v 2 v 3 v 5 o 1 -o 40 df cp load di 1 do 20 di 21 do 40 msM5259 v dd v ss v 2 v 3 v 5 o 1 -o 40 df cp load di 1 do 20 di 21 do 40 cc c cc ov rr rr r +5v
msM5259 ? semiconductor 14/18 application circuit for static display v 5 v 3 v dd v 2 o 1 cp di 1 df load v ss (gnd) com com msm4069 32-120h z duty 50% common signal data in shift clock load do 20 di 21 msM5259 o 40 do 40 +5v v 5 v 3 v dd v 2 o 1 cp di 1 df load v ss (gnd) do 20 di 21 msM5259 o 40 +5v 80-dot lcd panel seg 40 seg 1 seg 80 seg 41 the msM5259 is applicable to a static lcd by setting v 2 and v 5 at ground level, connecting v 3 to v dd and inputting common signal to df pin. this sample application circuit below is the case when the msM5259 is applied to an 80-bit lcd panel by connecting two msM5259s in series.
msM5259 ? semiconductor 15/18 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp56-p-910-0.65-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.36 typ. mirror finish
msM5259 ? semiconductor 16/18 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp56-p-910-0.65-l2 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.36 typ. spherical surface
msM5259 ? semiconductor 17/18 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp56-p-910-0.65-2k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.43 typ. mirror finish
msM5259 ? semiconductor 18/18 (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp56-p-910-0.65-2l2 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.43 typ. spherical surface

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